1. Field of the Invention
This invention relates to memory controllers and specifically to a technique for processing memory requests.
2. Background Information
Networking devices, such as routers and switches, often employ the use of a central processing unit (processor) to implement various functions supported by the networking device. Information, such as data and instructions, used by the processor is ususally kept in a memory subsystem that is typically connected to the processor via a communication bus. The memory subsystem often comprises a memory controller (controller) and a plurality of memory devices, such as random access memory (RAM). The memory controller acts as an interface between the memory devices and the processor and is typically configured to process memory requests issued by the processor. A memory request is a request that directs the memory controller to read or write information in the memory devices. A typical memory request contains an address that is used by the controller to determine the location of the information in the memory devices.
Advances in processor technology have led to the development of very high speed processors that are capable of operating at speeds much faster than the memory devices employed by the memory subsystem. As a consequence, the processor may become stalled while waiting for memory requests to complete, thus leading to a significant performance bottleneck between the processor and the memory subsystem. To avoid this bottleneck, systems are often designed to handle the processing of memory requests in an “out-of-order” fashion. Out-of-order processing means that requests may be processed in an order that is different than the order in which the requests were received. In other words, in a system that implements out-of-order processing, the results of requests are returned when the results are available and not necessarily in the order in which the requests were issued.
For example, assume a system that allows out-of-order processing comprises a processor connected to a memory subsystem that further comprises a memory controller and a plurality of memory devices. Further assume the processor issues two requests to read information located on two different memory devices and that the memory device associated with the first issued request is not available (i.e., not capable of servicing a request), whereas the memory device associated with the second issued request is available (i.e., capable of servicing a request). The memory controller processes the second request ahead of the first because the memory device associated with the second request is able to take the request immediately, whereas the memory device associated with the first request is not. All other things being equal, the results (i.e., information read) for the second request will likely be available ahead of the results for the first request, and since out-of-order processing is allowed, the results for the second request will be returned to the processor ahead of the results of the first request.
Systems that implement out-of-order processing typically track requests to match-up results with a particular request. One scheme often employed to track requests is to tag the request with a unique identifier, sometimes called a request identifier. In such schemes, the identifier is often assigned by the requestor. The identifier follows the request through the system and eventually is returned to the requestor along with the results of the request. The requestor can then use the identifier to match requests with results and perform whatever additional processing may be necessary, such as re-ordering results.
One problem associated with this scheme is that the entire system including the memory devices needs to be designed to accommodate the unique identifier. This may preclude the use of certain types of memory devices, such as certain standard “off-the-shelf” memory devices, as these devices may not be capable of accommodating the unique identifier. It would be desirable to have a simple yet effective technique for processing memory requests in a system that supports out-of-order processing that does not require the memory devices support a request identifier.